(1) Field of the Invention
The invention generally relates to an interconnection process used in semiconductor manufacturing and, more particularly, to a method of forming thick silicide films over ultra-shallow junctions in the fabrication of integrated circuits.
(2) Description of Prior Art
Silicide interconnection is formed on integrated circuits by first sputtering a metal such as titanium (Ti) over the surface of a completed structure. These structures are typically composed of doped silicon or silicon oxides or metal nitrides. When heated the metals over the doped silicon react with the silicon to form conductive compounds known as silicides, (TiSi2 for example). Because of this reaction, the doped silicon under the deposited metal is consumed at a rate approximately twice the thickness of the titanium layer. Metal over the silicon oxide or metal nitride areas remains unchanged and is easily removed using wet etching techniques. This leaves conductive lines and contacts in the silicide. In sub-quarter-micron MOSFET architectures, it is necessary to use ultra-shallow source and drain (S/D) regions. Ultra-shallow junctions limit the available silicon for consumption and therefore the thickness of silicide film must be reduced. Thinner silicides have the disadvantages of increased sheet resistance, film discontinuity, contact gouging at non-silicided locations, and high contact and parasitic resistances. For thin silicide films, C54 phase TiSi2 is preferred due to its high electrical conductivity. Triple-grain boundaries have a much higher energy state and promote C54 grain formation. Pre-amorphization implants (PAI) are often used to enhance C54 grain formation. This, however, results in undesirable effects such as implantation induced damage (e.g. transient enhanced diffusion in boron and junction leakage), film discontinuity and non-uniformity. For thick silicide films, C54 phase TiSi2 need not nucleate at triple-grain boundaries of C49 phase TiSi2 grains (hydrogen can nucleate at the grain boundaries), so the PAI is not required.
Other approaches for improving the silicide processing exist. U.S. Pat. No. 5,824,588 to Liu teaches a method that uses two gate sidewall spacers. The first spacer is higher than the second and acts as barrier to eliminate shorts between the source/drain and gate. U.S. Pat. No. 6,020,242 to Tsai et al. teaches a method where selected devices and circuit areas are blocked from the silicide process. U.S. Pat. No. 5,923,986 to Shen teaches a method incorporating an umbrella-like second spacer that prevents metal from being sputtered under the spacer, thereby eliminating shorts. U.S. Pat. No. 5,780,348 to Lin et al. teaches a method of forming parasitic spacers to reduce electrostatic discharge (ESD) problems. U.S. Pat. No. 5,882,973 to Gardner et al. teaches a method of forming variable width sidewall spacers,